Launched in 1994, this 32 bit processor of Motorola belongs to the fourth generation of 680×0 family. It’s immediate predecessor is Motorola 68040. This single chip processor features on chip demand paged memory management units, 8 Kilobyte of on-chip data and instruction caches, highly efficient floating point unit, a branch cache, dual issue super scalar execution and a deep pipeline. These features altogether enabled the processor to execute an instruction in less than a clock cycle.
68060 is a member of Motorola 680×0 family of 32 bit CISC microprocessors. Processors of this family were widely used in personal computers and workstations during 1980s and 1990s. At one point of time, 680×0 family was main rival to Intel’s x86 family. Many early versions of Apple Macintosh,SEGA Megadrive,Atari ST,Sinclair QL,Commodore Amiga featured 680×0 processors. 68060 is the last member of the 680×0 processor family. Network support is available for all 680×0 processors.
68060 is basically upgraded version of 68040. The minimum clock frequency of 68060 is 50MHz which is double of that of 68040 processor. 68060 could operate even at higher frequencies of 60MHz,66 MHz and 75MHz. 2.4 millions of transistors are used in 68060 processor. Advanced CMOS technology based on 0.5um triple level metal wafer process is employed in designing the processor. Due to this technology, 68060 is able to operate at 3.3 volts power supply. This is a significant improvement in power saving. Apart from power saving, it offers high performance computing. PC support is available for both power management and computing process.
The internal architecture of 68060 is of Harvard type. The data and instruction caches are designed to support simultaneous instruction fetch,operand write and operand read references on each clock cycle. A multi-port register file is coupled to this architecture to generate the necessary bandwidth to increase the throughput of the pipelines. The operand execution pipelines function in a lock stepped manner which made the program execution concurrent. The central part of the 68060 architecture is the integer unit pipeline. The super scalar micro architecture comprises two different pipelines. The first pipeline is a four stage instruction fetch pipeline that accesses the instruction stream. The second one is the dual four stage operand execution pipeline that executes the instructions. These two pipelines function independently with a first in first out buffer which provides decoupling mechanism. A branch cache reduces the latency effects of change of flow instructions by allowing the instruction fetch pipeline to detect changes in the instruction prefetch stream much before the execution. A super set of 68040 functionality is provided by the external bus interface of 68060. Transfer of 1,2,4 or 16 bytes in a single bus cycle is supported by maintaining 32 bit width on both of address and data bus. Motorola renders network support for resolving any problem related to architecture.
The instruction fetch pipeline fetches instructions and loads them into FIFO instruction buffer. Branch caches allows the instruction fetch pipeline to detect changes in the instruction stream based on the past execution history. This feature enabled the instruction fetch pipeline to provide a constant stream of instructions to the instruction buffer to increase the execution rate of operand execution pipeline. The pipeline organization is very complicated. If any problem occurs in the pipeline, it could only be resolved through the Computer Support from Motorola.
Network Support For 68060 Processor Based System
68060 processor is widely used in broadcast television graphics. Apart from this, many computers were designed based on this processor. Since this processor is used in so many applications, Motorola provides Tech support for all the 68060 processor based system. Apart from that Network Support is also provided by Motorola authorized vendors.